Description

R5 FPGA development kit using the Altera Stratix V GX FPGA provides high-speed operation and transmission with large capacity up to 622K LE.

FPGA Device

5SGXEA7N2F45C2N

• 622K Logic Elements (LEs)
• 57.16 Mbits Memory
• 256 Variable-precision DSP Blocks
• 512 18x18-bit Multipliers Blocks
• 28 Fractional PLLs and 4DLLs

• ＊FPGAs with higher LEs are also available. Please contact Terasic sales team.

FPGA Configuration

• MAX II CPLD EPM2210 System Controller for Fast Passive Parallel (FPP x16) Configuration
• On-board USB-Blaster II for use with Quartus II Programmer
  

Memory

• 128MB Flash with a 16-bit Data Bus
• 2MB SSRAM (1M x 16)
  

DDR3 SO-DIMM Socket

• Up to 8GB Capacity
• Maximum Clock Rate at 933 MHz
  

On-board Clocks

• 50 MHz Fixed Oscillator
• CDCM6208 Programmable PLL
• LMK04906B Programmable PLL
  

SMA Connectors

• SMA Connector Pair for Differential Clock Input and Output

Buttons, Switches and LEDs

• 4 User-controllable LEDs
• 4 Buttons for User-defined Inputs
• 4 Slide Switches for User-defined Inputs

PCI Express Gen 3 x4 Connector

• Support PCI Express Gen 3 x4 (8.0Gbps/lanes)
• High-speed Transceiver Channels up to 8 Gbps
• Support Downstream Mode

Two Serial ATA Ports

•  SATA 3.0 Standard at 6Gbps Signaling Rate

 Four FPGA Mezzanine Card (FMC) Connectors

• 2 HPC (high-pin count) FMC connectors up to 172 x2  Single-end I/O, 2 LPC (low-pin count) FMC connectors up to 76 x2 Single-end I/O
• 10 Transceiver Channels for each HPC FMC connector and 1Transceiver Channel for LPC each HPC FMC connector
• FMC VITA 57.1 Compliant
• Adjustable VADJ : 1.2V/1.5V/1.8V/2.5V/3.0V.
• Don’t support bidirectional LVDS due to Stratix V device only support single directional LVDS

One 40-pin Expansion Header

•     36 FPGA I/O pins; 4 power and ground lines
•     I/O standards: 3.3V

Power

• DC 12V Input
•