MYD-Y7Z010/007S Development Board
MYD-Y7Z010/007S  Development Board

Description of product

  • Package Lists
  • One MYD-Y7Z010 Board
    - One 1.5m cross Ethernet cable
    - One DB9 converting cable
    - One Power converting cable
    - One 12V/1.25A Power adapter
    - One product disk 
    (including user manual, 
    base board schematic in PDF format, 
    datasheets and software package)
  • MYIR provides a development board MYD-Y7Z010/007S for evaluating the MYC-Y7Z010/007S CPU Module, which employs the MYC-Y7Z010/007S as the controller board by populating the CPU Module on its base board through 1.27mm pitch 180-pin stamp-hole (Castellated-Hole) interface. The base board has extended a rich set of peripheral interfaces including serial ports, USB Host port, three Gigabit Ethernet ports, CAN, TF card slot, JTAG, etc. One 2.54mm pitch 2 x 25-pin expansion headeris on the base board to let more GPIOs available for further extension. MYIR offers an optional MYD-7Z010/007S IO CAPE to connect to this expansion header to extend many peripherals and signals like HDMI, LCD, camera and Pmod to help user explore more functions. The 7-inch LCD Module with capacitive touch screen as well as MY-CAM011B camera module from MYIR can be supported through the IO Cape. 


    MYD-Y7Z010/007S Development Board

    MYD-Y7Z010/007S Board in the Video


    Mechanical Parameters

    • Dimensions: 75mm x 50mm (10-layer design)
    • Power supply: 5V
    • Working temp.: -40~85 Celsius (industrial grade)


      • Xilinx XC7Z010-1CLG400I (Zynq-7010) or XC7Z007S-1CLG400I (Zynq-7007S) ARM® Cortex™-A9 MPCore processo
        - 667MHz dual-core processor (up to 866MHz, for XC7Z010) 
        - 667MHz single-core processor (up to 766MHz, for XC7Z007S)
        - Integrated Artix-7 class FPGA subsystem
        with 28K logic cells, 17,600 LUTs, 80 DSP slices (for XC7Z010)
        with 23K logic cells, 14,400 LUTs, 66DSP slices (for XC7Z007S)
        - NEON™ & Single / Double Precision Floating Point for each processor
        - Supports a Variety of Static and Dynamic Memory Interfaces


    • 512MB DDR3 (2 x 256MB, 32-bit)
    • 4GB eMMC
    • 16MB QSPI Flash

    Peripherals and Signals Routed to Pins

    • 10/100/1000M Ethernet PHY
    • External watchdog
    • Three LEDs
      - One red LED for power indicator
      - One green LED for FPGA program done indicator
      - One flashing green LED for system indicator 
    • 1.27mm pitch 180-pin Stamp Hole Expansion Interface brings out below signals:
      - One Gigabit Ethernet
      - One USB
      - Two Serial ports 
      - Two I2C
      - Two CAN BUS
      - Two SPI
      * Serial ports, I2C, CAN and SPI signals in PS part can be implemented through PL pins via Emio.
      - Two ADC (16-channel ADC brought out through PL pins)
      - One SDIO

    OS Support

    • Linux 3.15.0