Texas Instruments SN65DSI86/SN65DSI86-Q1 DSI to embedded DisplayPort (eDP) Bridge features a dual-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1.5Gbps per lane and a maximum input bandwidth of 12Gbps. The bridge decodes MIPI DSI 18bpp RGB666 and 24bpp RGB888 packets. The device also converts the formatted video data-stream to a DisplayPort with up to four lanes at either 1.62Gbps, 2.16Gbps, 2.43Gbps, 2.7Gbps, 3.24Gbps, 4.32Gbps, or 5.4Gbps. The SN65DSI86/SN65DSI86-Q1 is well suited for WQXGA (2560 × 1600) at 60 frames per second, as well as 3D Graphics at 4K and true HD (1920 × 1080) resolutions at an equivalent 120fps with up to 24bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and DisplayPort interfaces. The Texas Instruments SN65DSI86-Q1 devices are AEC-Q100 qualified for automotive applications.