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74LS109, Dual J-K Positive-edge-triggered Flip-Flops

General Description
This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the J and K inputs may be changed while the clock is HIGH or LOW as long as setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.

*Image shown is a representation only.

TT-ECK-4553
in stock INR 27.14
ELECTRON COMPONENT
1 1

74LS109 – Dual J-K Positive-edge-triggered Flip-Flops

Sku: TT-ECK-4553
₹27.14


Sold By: tenettech
Features
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Description of product

74LS109, Dual J-K Positive-edge-triggered Flip-Flops

General Description
This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the J and K inputs may be changed while the clock is HIGH or LOW as long as setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.

*Image shown is a representation only.