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5ff80410477578563c0cb282 IC CLK BUF 400MHZ 1CIRC 32WQFN https://cdn1.storehippo.com/s/59c9e4669bd3e7c70c5f5e6c/5ff80411477578563c0cb2c7/webp/32-wqfn-exposed-pad-rtv.webp

Description:

The LMK00334 device is a 4-output HCSL fanout buffer intended for high-frequency, low-jitter clock, data distribution, and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of 2 HCSL outputs and one LVCMOS output. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00334 operates from a 3.3-V core supply and 3 independent 3.3-V or 2.5-V output supplies.

Features:

  • 3:1 Input Multiplexer
    – Two Universal Inputs Operate up to 400 MHz
    and Accept LVPECL, LVDS, CML, SSTL,
    HSTL, HCSL, or Single-Ended Clocks
    – One Crystal Input Accepts a 10- to 40-MHz
    Crystal or Single-Ended Clock
  • Two Banks With 2 Differential Outputs Each
    – HCSL, or Hi-Z (Selectable)
    – Additive RMS Phase Jitter for PCIe
    Gen3/Gen4 at 100 MHz:
    – 30 fs RMS (typical)
  • High PSRR: –72 dBc at 156.25 MHz
  • LVCMOS Output With Synchronous Enable Input
  • Pin-Controlled Configuration
  • VCC Core Supply: 3.3 V ± 5%
  • 3 Independent VCCO Output Supplies: 3.3 V/2.5 V
    ± 5%
CS-296-37190-1-ND
in stock INR 269
Texas Instruments
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IC CLK BUF 400MHZ 1CIRC 32WQFN

Description of product

Description:

The LMK00334 device is a 4-output HCSL fanout buffer intended for high-frequency, low-jitter clock, data distribution, and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of 2 HCSL outputs and one LVCMOS output. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00334 operates from a 3.3-V core supply and 3 independent 3.3-V or 2.5-V output supplies.

Features:

  • 3:1 Input Multiplexer
    – Two Universal Inputs Operate up to 400 MHz
    and Accept LVPECL, LVDS, CML, SSTL,
    HSTL, HCSL, or Single-Ended Clocks
    – One Crystal Input Accepts a 10- to 40-MHz
    Crystal or Single-Ended Clock
  • Two Banks With 2 Differential Outputs Each
    – HCSL, or Hi-Z (Selectable)
    – Additive RMS Phase Jitter for PCIe
    Gen3/Gen4 at 100 MHz:
    – 30 fs RMS (typical)
  • High PSRR: –72 dBc at 156.25 MHz
  • LVCMOS Output With Synchronous Enable Input
  • Pin-Controlled Configuration
  • VCC Core Supply: 3.3 V ± 5%
  • 3 Independent VCCO Output Supplies: 3.3 V/2.5 V
    ± 5%