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# 2514/U, 7th 'A' Main Road, Opp. to BBMP Swimming Pool, Hampinagar, Vijayanagar 2nd Stage. Bangalore, IN
+918023404924 https://cdn1.storehippo.com/s/59c9e4669bd3e7c70c5f5e6c/ms.settings/5256837ccc4abf1d39000001/webp/59dafe26aef6e1d20402c4c3-480x480.png" info@tenettech.com
6050838052e2a4766f25d12a DRAM 8G 1Gx8 933MHz 1.35V DDR3 ET https://cdn1.storehippo.com/s/59c9e4669bd3e7c70c5f5e6c/6050838052e2a4766f25d12c/webp/alliance_fbga_78_t.png

DDR3L SDRAM

Alliance Memory DDR3L SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock-cycle data transfer at the internal DRAM core and eight corresponding  n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.

TT-MU-913-AS4C1G8D3LA10BCN
in stock INR 7873.20072
Alliance Memory
1 1
DRAM 8G 1Gx8 933MHz 1.35V DDR3 ET

DRAM 8G 1Gx8 933MHz 1.35V DDR3 ET

Sku: TT-MU-913-AS4C1G8D3LA10BCN
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₹7,873.2
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Description of product

DDR3L SDRAM

Alliance Memory DDR3L SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock-cycle data transfer at the internal DRAM core and eight corresponding  n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.

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