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5ff008668d1d14cd7071943c Digital Signal Processors & Controllers - DSP, DSC Fixed-Point Digital Signal Processor https://cdn1.storehippo.com/s/59c9e4669bd3e7c70c5f5e6c/5ff00794df99c055481f2e51/webp/nfbga_zay-144_dsl.webp

Description:

These devices are members of TI's C5000™ fixed-point Digital Signal Processor (DSP) product family and are designed for low-power applications.The fixed-point DSP is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

Applications:

  • Wireless Audio Devices (for example, Headsets, Microphones, Speakerphones)
  • Echo Cancellation Headphones
  • Portable Medical Devices
  • Voice Applications
  • Industrial Controls
  • Fingerprint Biometrics
  • Software-defined Radio

Datasheet

TT-MUS-595-S320C5535AZAY10
in stockINR 617
TI
1 1
XYZ Blog title
ABC Blog title here
Digital Signal Processors & Controllers - DSP, DSC Fixed-Point Digital Signal Processor

Description of product

Description:

These devices are members of TI's C5000™ fixed-point Digital Signal Processor (DSP) product family and are designed for low-power applications.The fixed-point DSP is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

Applications:

  • Wireless Audio Devices (for example, Headsets, Microphones, Speakerphones)
  • Echo Cancellation Headphones
  • Portable Medical Devices
  • Voice Applications
  • Industrial Controls
  • Fingerprint Biometrics
  • Software-defined Radio

Datasheet