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604ef2ae6f2792b2d398e579 Data Conversion IC Development Tools ADC12QJ1600-Q1 8-ch (two synchronized 4-ch) 12-bit 1.6-GSPS JESD204C interface ADC evaluation module //cdn.storehippo.com/s/59c9e4669bd3e7c70c5f5e6c/604ef2ae6f2792b2d398e57b/webp/tsw12qj1600evm_dsl.png

TSW12QJ1600 ADC Evaluation Module (EVM)

Texas Instruments TSW12QJ1600EVM ADC Evaluation Module (EVM) is used to evaluate the ADC12QJ1600-Q1 analog-to-digital converter (ADC) with different front-end options. ADC12QJ1600-Q1 is a 12-bit ADC capable of operating at sampling rates up to 1.6 Giga samples per second (GSPS) with four analog input channels. This evaluation module has two ADC12QJ1600-Q1 devices on the same printed circuit board (PCB). These can be used to demonstrate multiple ADC synchronizations, deterministic latency, and test the performance of the ADC with various front-end options (AC-coupled transformer; DC-coupled option with LMH32401). The design also demonstrates how the clocking scheme can be simplified by daisy-chaining the PLL reference output (PLLREFO+, PLLREFO-) from one ADC to another, eliminating the need for the clock-distribution chip that is usually needed by JESD devices.

TT-MU-595-TSW12QJ1600EVM
in stock INR 741664.843
Texas Instruments
1 1

Data Conversion IC Development Tools ADC12QJ1600-Q1 8-ch (two synchronized 4-ch) 12-bit 1.6-GSPS JESD204C interface ADC evaluation module

Sku: TT-MU-595-TSW12QJ1600EVM
₹741,664.84


Sold By: tenettech
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Description of product

TSW12QJ1600 ADC Evaluation Module (EVM)

Texas Instruments TSW12QJ1600EVM ADC Evaluation Module (EVM) is used to evaluate the ADC12QJ1600-Q1 analog-to-digital converter (ADC) with different front-end options. ADC12QJ1600-Q1 is a 12-bit ADC capable of operating at sampling rates up to 1.6 Giga samples per second (GSPS) with four analog input channels. This evaluation module has two ADC12QJ1600-Q1 devices on the same printed circuit board (PCB). These can be used to demonstrate multiple ADC synchronizations, deterministic latency, and test the performance of the ADC with various front-end options (AC-coupled transformer; DC-coupled option with LMH32401). The design also demonstrates how the clocking scheme can be simplified by daisy-chaining the PLL reference output (PLLREFO+, PLLREFO-) from one ADC to another, eliminating the need for the clock-distribution chip that is usually needed by JESD devices.